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1 LT1218/lt1219 n rail-to-rail input and output n 90 m v v os(max) for v cm = v C to v + n high common mode rejection ratio: 97db min n c-load tm stable version (lt1219) n high a vol : 500v/mv minimum driving 10k w load n wide supply range: 2v to 15v (LT1218/lt1219) 2v to 5v (LT1218l/lt1219l) n shutdown mode: i s < 30 m a n low supply current: 420 m a max n low input bias current: 18na typical n 300khz gain-bandwidth product (LT1218) n slew rate: 0.10v/ m s (LT1218) features descriptio n u the lt ? 1218/lt1219 are bipolar op amps which combine rail-to-rail input and output operation with precision speci- fications. unlike other rail-to-rail amplifiers, the LT1218/ lt1219s input offset voltage is a low 90 m v across the entire rail-to-rail input range, not just a portion of it. using a patented technique, both input stages of the LT1218/ lt1219 are trimmed: one at the negative supply and the other at the positive supply. the resulting common mode rejection of 97db minimum is much better than other rail- to-rail input op amps. a minimum open-loop gain of 500v/mv into a 10k load virtually eliminates all gain error. the LT1218 has conventional compensation which assures stability for capacitive loads of 1000pf or less. the lt1219 has compensation that requires the use of a 0.1 m f output capacitor, which improves the amplifiers supply rejection and reduces output impedance at high frequencies. the output capacitors filtering action also reduces high frequency noise, which is beneficial when driving a/d converters. high and low voltage versions of the devices are offered. operation is specified for 3v, 5v and 5v supplies for the LT1218l/lt1219l and 3v, 5v and 15v for the LT1218/ lt1219. applicatio n s u n driving a/d converters n test equipment amplifiers n mux amplifiers precision rail-to-rail input and output op amps c-load is a trademark of linear technology corporation. , ltc and lt are registered trademarks of linear technology corporation. voltage follower input to output error mux amplifier typical applicatio n u + + LT1218l LT1218l v out v in1 v in2 input select 5v 5v 74hco4 1218/19 ?ta01 shdn maximum in to out error = 110 v for 0.05v v in 4.8v r l = 10k shdn input voltage (v) 0 ? error ? (mv) 1234 LT1218/19 ?ta02 5 v s = 5v a v = 1 no load 10 1.0 0.1 0.01 0.05 4.95 max error = 110 v 0.05v v in 4.8v
2 LT1218/lt1219 absolute m axi m u m ratings w ww u package/order i n for m atio n w u u supply voltage LT1218/lt1219 ................................................. 18v LT1218l/lt1219l ............................................... 8v input current ...................................................... 15ma output short-circuit duration (note 1) ......... continuous operating temperature range ................ C 40 c to 85 c specified temperature range (note 3) ... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c junction temperature........................................... 150 c lead temperature (soldering, 10 sec).................. 300 c order part number LT1218cn8 LT1218cs8 LT1218lcn8 LT1218lcs8 lt1219cn8 lt1219cs8 lt1219lcn8 lt1219lcs8 s8 part marking 1 2 3 4 8 7 6 5 top view v os trim in +in v v os trim v + out shdn n8 package 8-lead pdip s8 package 8-lead plastic so t jmax = 150 c, q ja = 130 c/ w (n8) t jmax = 150 c, q ja = 190 c/ w (s8) 1218 1219 1218l 1219l consult factory for industrial and military grades. symbol parameter conditions min typ max units v os input offset voltage v cm = v + 25 90 m v v cm = v C 25 90 m v d v os input offset voltage shift v cm = v C to v + 15 70 m v i b input bias current v cm = v + 30 70 na v cm = v C C 70 C 18 na d i b input bias current shift v cm = v C to v + 50 140 na i os input offset current v cm = v + 518na v cm = v C 218na d i os input offset current shift v cm = v C to v + 518na e n input noise voltage density f = 1khz 33 nv/ ? hz i n input noise current density f = 1khz 0.09 pa/ ? hz a vol large-signal voltage gain v s = 5v, v o = 50mv to 4.8v, r l = 10k 250 1000 v/mv v s = 3v, v o = 50mv to 2.8v, r l = 10k 200 750 v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + 97 110 db v s = 3v, v cm = v C to v + 92 106 db psrr power supply rejection ratio v s = 2.3v to 12v, v cm = 0v, v o = 0.5v 90 100 db v ol output voltage swing low no load 4 12 mv i sink = 0.5ma 45 90 mv i sink = 2.5ma 120 240 mv v oh output voltage swing high no load v + C 0.012 v + C 0.003 v i source = 0.5ma v + C 0.130 v + C 0.065 v i source = 2.5ma v + C 0.400 v + C 0.210 v i sc short-circuit current v s = 5v 5 10 ma v s = 3v 4 7 ma i s supply current v s = 5v 370 420 m a v s = 3v 370 410 m a positive supply current, shdn v s = 5v, v shdn = 0v 9 30 m a v s = 3v, v shdn = 0v 6 20 m a t a = 25 c, v s = 5v, 0v; v s = 3v, 0v; v cm = v o = half supply, v shdn = v + , unless otherwise noted. electrical characteristics
3 LT1218/lt1219 electrical characteristics t a = 25 c, v s = 5v, 0v; v s = 3v, 0v; v cm = v o = half supply, v shdn = v + , unless otherwise noted. symbol parameter conditions min typ max units sr slew rate (LT1218/LT1218l) a v = C 1 0.10 v/ m s (lt1219/lt1219l) a v = C 1 0.05 v/ m s gbw gain bandwidth product (LT1218/LT1218l) a v = 1000 0.30 mhz (lt1219/lt1219l) a v = 1000 0.15 mhz symbol parameter conditions min typ max units v os input offset voltage v cm = v + l 75 200 m v v cm = v C l 75 200 m v v os tc input offset drift (note 2) l 13 m v/ c d v os input offset voltage shift v cm = v C to v + l 25 80 m v i b input bias current v cm = v + l 30 75 na v cm = v C l C 75 C 18 na d i b input bias current shift v cm = v C to v + l 50 150 na i os input offset current v cm = v + l 525na v cm = v C l 325na d i os input offset current shift v cm = v C to v + l 525na a vol large-signal voltage gain v s = 5v, v o = 50mv to 4.8v, r l = 10k l 250 1000 v/mv v s = 3v, v o = 50mv to 2.8v, r l = 10k l 150 750 v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + l 96 104 db v s = 3v, v cm = v C to v + l 91 106 db psrr power supply rejection ratio v s = 2.3v to 12v, v cm = 0v, v o = 0.5v l 88 100 db v ol output voltage swing low no load l 414mv i sink = 0.5ma l 45 100 mv i sink = 2.5ma l 130 290 mv v oh output voltage swing high no load l v + C 0.014 v + C 0.004 v i source = 0.5ma l v + C 0.150 v + C 0.075 v i source = 2.5ma l v + C 0.480 v + C 0.240 v i sc short-circuit current v s = 5v l 47 ma v s = 3v l 36 ma i s supply current v s = 5v l 370 485 m a v s = 3v l 370 475 m a positive supply current, shdn v s = 5v, v shdn = 0v l 936 m a v s = 3v, v shdn = 0v l 626 m a 0 c t a 70 c, v s = 5v, 0v; v s = 3v, 0v; v cm = v o = half supply, v shdn = v + , unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage v cm = v + C 0.15 l 400 m v v cm = v C + 0.15 l 400 m v v os tc input offset drift (note 2) l 14 m v/ c d v os input offset voltage shift v cm = v + C 0.15 to v C + 0.15 l 30 105 m v i b input bias current v cm = v + C 0.15 l 80 na v cm = v C + 0.15 l C80 na d i b input bias current shift v cm = v + C 0.15 to v C + 0.15 l 160 na i os input offset current v cm = v + C 0.15 l 40 na v cm = v C + 0.15 l 40 na d i os input offset current shift v cm = v + C 0.15 to v C + 0.15 l 40 na C40 c t a 85 c, v s = 5v, 0v; v s = 3v, 0v; v cm = v o = half supply, v shdn = v + , unless otherwise noted. (note 3)
4 LT1218/lt1219 electrical characteristics symbol parameter conditions min typ max units a vol large-signal voltage gain v s = 5v, v o = 50mv to 4.8v, r l = 10k l 150 500 v/mv v s = 3v, v o = 50mv to 2.8v, r l = 10k l 100 500 v/mv cmrr common mode rejection ratio v s = 5v, v cm = v + C 0.15 to v C + 0.15 l 93 102 db v s = 3v, v cm = v + C 0.15 to v C + 0.15 l 88 100 db psrr power supply rejection ratio v s = 2.3v to 12v, v cm = 0v, v o = 0.5v l 86 100 db v ol output voltage swing low no load l 515mv i sink = 0.5ma l 50 105 mv i sink = 2.5ma l 130 300 mv v oh output voltage swing high no load l v + C 0.015 v + C 0.004 mv i source = 0.5ma l v + C 0.160 v + C 0.070 mv i source = 2.5ma l v + C 0.500 v + C 0.250 mv i sc short-circuit current v s = 5v l 47 ma v s = 3v l 37 ma i s supply current v s = 5v l 410 505 m a v s = 3v l 400 495 m a positive supply current, shdn v s = 5v, v shdn = 0v l 15 50 m a v s = 3v, v shdn = 0v l 13 40 m a C40 c t a 85 c, v s = 5v, 0v; v s = 3v, 0v; v cm = v o = half supply, v shdn = v + , unless otherwise noted. (note 3) LT1218l/lt1219l only; t a = 25 c, v s = 5v, v cm = 0v, v o = 0v, v shdn = 5v, unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage v cm = v + 35 140 m v v cm = v C 35 140 m v d v os input offset voltage shift v cm = v C to v + 20 70 m v i b input bias current v cm = v + 30 70 na v cm = v C C 70 C 18 na d i b input bias current shift v cm = v C to v + 50 140 na i os input offset current v cm = v + 518na v cm = v C 218na d i os input offset current shift v cm = v C to v + 518na a vol large-signal voltage gain v o = C 4.7v to 4.7v, r l = 10k 500 2800 v/mv v o = C 4.5v to 4.5v, r l = 2k 300 1300 v/mv cmrr common mode rejection ratio v cm = v C to v + 103 114 db v ol output voltage swing low no load v C + 0.004 v C + 0.012 v i sink = 0.5ma v C + 0.045 v C + 0.090 v i sink = 5ma v C + 0.180 v C + 0.525 v v oh output voltage swing high no load v + C 0.012 v + C 0.003 v i source = 0.5ma v + C 0.130 v + C 0.065 v i source = 5ma v + C 0.800 v + C 0.350 v i sc short-circuit current 6 12 ma i s supply current 400 430 m a positive supply current, shdn v shdn = 0v 10 40 m a sr slew rate (LT1218/LT1218l) a v = C 1, r l = open, v o = 3.5v 0.06 0.10 v/ m s (lt1219/lt1219l) a v = C 1, r l = open, v o = 3.5v 0.03 0.05 v/ m s gbw gain-bandwidth product (LT1218/LT1218l) a v = 1000 0.2 0.30 mhz (lt1219/lt1219l) a v = 1000 0.1 0.15 mhz
5 LT1218/lt1219 electrical characteristics LT1218l/lt1219l only; 0 c t a 70 c, v s = 5v, v cm = 0v, v o = 0v, v shdn = 5v, unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage v cm = v + l 100 250 m v v cm = v C l 100 250 m v d v os input offset voltage shift v cm = v C to v + l 30 90 m v i b input bias current v cm = v + l 30 75 na v cm = v C l C 75 C 18 na d i b input bias current v cm = v C to v + l 50 150 na i os input offset current v cm = v + l 525na v cm = v C l 325na d i os input offset current shift v cm = v C to v + l 520na a vol large-signal voltage gain v o = C 4.7v to 4.7v, r l = 10k l 375 2800 v/mv v o = C 4.5v to 4.5v, r l = 2k l 275 1300 v/mv cmrr common mode rejection ratio v cm = v C to v + l 100 110 db v ol output voltage swing low no load l v C + 0.004 v C + 0.014 v i sink = 0.5ma l v C + 0.045 v C + 0.100 v i sink = 5ma l v C + 0.200 v C + 0.580 v v oh output voltage swing high no load l v + C 0.014 v + C 0.004 v i source = 0.5ma l v + C 0.150 v + C 0.075 v i source = 5ma l v + C 0.920 v + C 0.450 v i sc short-circuit current l 510 ma i s supply current l 400 495 m a positive supply current, shdn v shdn = 0v l 11 54 m a symbol parameter conditions min typ max units v os input offset voltage v cm = v + C 0.15 l 125 500 m v v cm = v C + 0.15 l 125 500 m v d v os input offset voltage shift v cm = v + C 0.15 to v C + 0.15 l 35 120 m v i b input bias current v cm = v + C 0.15 l 80 na v cm = v C + 0.15 l C80 na d i b input bias current v cm = v + C 0.15 to v C + 0.15 l 160 na i os input offset current shift v cm = v + C 0.15 l 40 na v cm = v C + 0.15 l 40 na d i os input offset current shift v cm = v + C 0.15 to v C + 0.15 l 40 na a vol large-signal voltage gain v o = C 4.7v to 4.7v, r l = 10k l 300 2000 v/mv v o = C 4.5v to 4.5v, r l = 2k l 200 600 v/mv cmrr common mode rejection ratio v cm = v + C 0.15 to v C + 0.15 l 98 109 db v ol output voltage swing low no load l v C + 0.005 v C + 0.015 v i sink = 0.5ma l v C + 0.050 v C + 0.105 v i sink = 2.5ma l v C + 0.200 v C + 0.620 v v oh output voltage swing high no load l v + C 0.015 v + C 0.004 v i source = 0.5ma l v + C 0.160 v + C 0.070 v i source = 2.5ma l v + C 1.000 v + C 0.400 v i sc short-circuit current l 510 ma i s supply current l 420 525 m a positive supply current, shdn v shdn = 0v l 18 60 m a LT1218l, lt1219l only; C 40 c t a 85 c, v s = 5v; v cm = 0v, v o = 0v, v shdn = 5v, unless otherwise noted. (note 3)
6 LT1218/lt1219 electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = v + 85 200 m v v cm = v C 85 200 m v d v os input offset voltage shift v cm = v C to v + 30 70 m v i b input bias current v cm = v + 30 70 na v cm = v C C 70 C 18 na d i b input bias current v cm = v C to v + 50 140 na i os input offset current v cm = v + 518na v cm = v C 218na d i os input offset current shift v cm = v C to v + 518na a vol large-signal voltage gain v o = C 14.7v to 14.7v, r l = 10k 1000 4000 v/mv v o = C 10v to 10v, r l = 2k 500 2000 v/mv cmrr common mode rejection ratio v cm = v C to v + 113 120 db psrr power supply rejection ratio v s = 5v to 15v 100 110 db v ol output voltage swing low no load v C + 0.004 v C + 0.012 v i sink = 0.5ma v C + 0.045 v C + 0.090 v i sink = 5ma v C + 0.270 v C + 0.525 v v oh output voltage swing high no load v + C 0.012 v + C 0.003 v i source = 0.5ma v + C 0.130 v + C 0.065 v i source = 5ma v + C 0.800 v + C 0.580 v i sc short-circuit current 10 20 ma i s supply current 425 550 m a positive supply current, shdn v shdn = 0v 15 40 m a sr slew rate (LT1218/LT1218l) a v = C 1 0.10 v/ m s (lt1219/lt1219l a v = C 1 0.05 v/ m s gbw gain bandwidth product (LT1218/LT1218l) a v = 1000 0.28 mhz (lt1219/lt1219l) a v = 1000 0.15 mhz LT1218/lt1219 only; t a = 25 c, v s = 15v, v cm = 0v, v o = 0v, v shdn = 15v, unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage v cm = v + l 120 300 m v v cm = v C l 120 300 m v d v os input offset voltage shift v cm = v C to v + l 50 105 m v i b input bias current v cm = v + l 30 75 na v cm = v C l C 75 C 18 na d i b input bias current v cm = v C to v + l 50 150 na i os input offset current v cm = v + l 525na v cm = v C l 325na d i os input offset current shift v cm = v C to v + l 520na a vol large-signal voltage gain v o = C 14.7v to 14.7v, r l = 10k l 750 3000 v/mv v o = C 10v to 10v, r l = 2k l 500 1500 v/mv cmrr common mode rejection ratio v cm = v C to v + l 109 114 db psrr power supply rejection ratio v s = 5v to 15v l 97 110 db v ol output voltage swing low no load l v C + 0.004 v C + 0.014 v i sink = 0.5ma l v C + 0.045 v C + 0.100 v i sink = 5ma l v C + 0.310 v C + 0.580 v v oh output voltage swing high no load l v + C 0.014 v + C 0.003 v i source = 0.5ma l v + C 0.150 v + C 0.075 v i source = 5ma l v + C 0.920 v + C 0.700 v LT1218/lt1219 only; 0 c t a 70 c, v s = 15v, v cm = 0v, v o = 0v, v shdn = 15v, unless otherwise noted.
7 LT1218/lt1219 electrical characteristics LT1218/lt1219 only; 0 c t a 70 c, v s = 15v, v cm = 0v, v o = 0v, v shdn = 15v, unless otherwise noted. symbol parameter conditions min typ max units i sc short-circuit current l 817 ma i s supply current l 450 600 m a positive supply current, shdn v shdn = 0v l 20 54 m a symbol parameter conditions min typ max units v os input offset voltage v cm = v + C 0.15 l 150 600 m v v cm = v C + 0.15 l 150 600 m v d v os input offset voltage shift v cm = v + C 0.15 to v C + 0.15 l 50 165 m v i b input bias current v cm = v + C 0.15 l 80 na v cm = v C + 0.15 l C80 na d i b input bias current v cm = v + C 0.15 to v C + 0.15 l 160 na i os input offset current v cm = v + C 0.15 l 40 na v cm = v C + 0.15 l 40 na d i os input offset current shift v cm = v + C 0.15 to v C + 0.15 l 40 na a vol large-signal voltage gain v o = C 14.7v to 14.7v, r l = 10k l 500 3000 v/mv v o = C 10v to 10v, r l = 2k l 400 1000 v/mv cmrr common mode rejection ratio v cm = v + C 0.15 to v C + 0.15 l 105 114 db psrr power supply rejection ratio v s = 5v to 15v l 96 110 db v ol output voltage swing low no load l v C + 0.005 v C + 0.015 v i sink = 0.5ma l v C + 0.050 v C + 0.105 v i sink = 2.5ma l v C + 0.200 v C + 0.620 v v oh output voltage swing high no load l v + C 0.015 v + C 0.004 v i source = 0.5ma l v + C 0.160 v + C 0.070 v i source = 2.5ma l v + C 1.000 v + C 0.400 v i sc short-circuit current l 514 ma i s supply current l 650 m a positive supply current, shdn v shdn = 0v l 60 m a LT1218, lt1219 only; C 40 c t a 85 c, v s = 15v; v cm = 0v = v o = 0v, v shdn = 15v, unless otherwise noted. (note 3) note 2: this parameter is not 100% tested. note 3: the LT1218/lt1219 are designed, characterized and expected to meet these extended temperature limits, but are not tested at C40 c and 85 c. guaranteed i grade part are available: consult factory. the l denotes specifications which apply over the full operating temperature range. note 1: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely.
8 LT1218/lt1219 typical perfor m a n ce characteristics u w v os distribution, v cm = 0v input offset voltage ( v) percent of units (%) 30 25 20 15 10 5 0 60 20 20 60 LT1218/19 ?tpc01 100 100 v s = 5v, 0v v cm = 0v input offset voltage ( v) percent of units (%) 30 25 20 15 10 5 0 60 20 20 60 LT1218/19 ?tpc03 100 100 v s = 5v, 0v v cm = 5v v os distribution, v cm = 5v input offset voltage ( v) 100 percent of units (%) 40 35 30 25 20 15 10 5 0 60 LT1218/19 ?tpc02 ?0 ?0 20 100 v s = 5v, 0v v cm = 0v to 5v v os shift, v cm = 0v to 5v supply current vs temperature input bias current vs common mode voltage minimum supply voltage temperature ( c) ?0 supply current ( a) 500 400 300 200 100 0 0 40 60 LT1218/19 ?tpc04 ?0 20 80 100 v s = 15v v s = 2.5v common mode voltage (v) ? input bias current (na) 7 LT1218/19 ?tpc06 1 3 5 50 25 0 25 ?0 0 2 4 6 t a = 25 c t a = 85 c t a = 40 c v s = 5v, 0v t a = 25 c total supply voltage (v) 1.0 change in offset voltage ( v) 200 150 100 50 0 ?0 1.5 2.0 2.5 LT1218/19 ?tpc05 3.5 3.0 4.0 4.5 5.0 t a = 40 c t a = 25 c t a = 85 c load current (ma) 0.001 0.001 saturation voltage (v) 0.1 10 0.1 0.01 10 LT1218/19 ?tpc07 0.01 1 1 t a = 25 c t a = 85 c t a = 40 c v s = 5v, 0v output saturation voltage vs load current (output low) 0.1hz to 10hz output voltage noise output saturation voltage vs load current (output high) load current (ma) 0.001 0.001 saturation voltage (v) 0.1 10 0.1 0.01 10 LT1218/19 ?tpc08 0.01 1 1 t a = 25 c t a = 85 c t a = 40 c v s = 5v, 0v time (1s/div) output voltage (400nv/div) LT1218/19 ?tpc09 v s = 2.5v v cm = 0v
9 LT1218/lt1219 typical perfor m a n ce characteristics u w LT1218 gain and phase shift vs frequency frequency (khz) voltage gain (db) phase shift (deg) 70 60 50 40 30 20 10 0 10 20 ?0 140 120 100 80 60 40 20 0 20 40 ?0 1 100 1000 10000 LT1218/19 ?tpc12 10 phase gain v s = 2.5v lt1219 gain and phase shift vs frequency frequency (khz) voltage gain (db) phase shift (deg) 70 60 50 40 30 20 10 0 10 20 ?0 140 120 100 80 60 40 20 0 20 40 ?0 1 100 1000 10000 LT1218/19 ?tpc13 10 phase gain v s = 2.5v c l = 0.1 f noise current spectrum frequency (hz) 1 current noise (pa/ ? hz) 2.5 2.0 1.5 1.0 0.5 0 10 100 1000 LT1218/19 ?tpc11 v s = 5v, 0v v cm = 4v v cm = 2.5v noise voltage spectrum LT1218 gain bandwidth and phase margin vs supply voltage supply voltage (v) 0 frequency (khz) phase margin (deg) 15 25 LT1218/19 ?tpc 510 20 400 350 300 250 200 150 100 50 0 80 70 60 50 40 30 20 10 0 30 phase margin gbw LT1218 common mode rejection ratio vs frequency frequency (khz) 1 common mode rejection ratio (db) 100 90 80 70 60 50 40 30 20 10 0 10 100 1000 LT1218/19 ?tpc15 v s = 2.5v lt1219 power supply rejection ratio vs frequency frequency (khz) 1 power supply rejection ratio (db) 100 90 80 70 60 50 40 30 20 10 0 10 100 1000 LT1218/19 ?tpc16 v s = 2.5v positive supply negative supply frequency (hz) 1 noise voltage (nv/ ? hz) 100 90 80 70 60 50 40 30 20 10 0 10 100 1000 LT1218/19 ?tpc10 v s = 5v, 0v v cm = 4v v cm = 2.5v
10 LT1218/lt1219 typical perfor m a n ce characteristics u w LT1218 power supply rejection ratio vs frequency LT1218 closed loop output impedance vs frequency lt1219 closed loop output impedance vs frequency frequency (khz) 1 power supply rejection ratio (db) 100 90 80 70 60 50 40 30 20 10 0 10 100 1000 LT1218/19 ?tpc17 v s = 2.5v positive supply negative supply frequency (khz) 0.1 0.1 output impedance ( ) 10 1000 1 10 100 1000 LT1218/19 ?tpc18 1.0 100 a v = 10 a v = 1 v s = 2.5v frequency (khz) 0.1 0.1 output impedance ( ) 10 1000 1 10 100 1000 LT1218/19 ?tpc19 1.0 100 v s = 2.5v c l = 0.1 f a v = 10 a v = 1 LT1218 capacitive load handling lt1219 overshoot vs load current, v s = 2.5v lt1219 overshoot vs load current, v s = 15v load current (ma) ?0 overshoot (%) 5 LT1218/19 ?tpc21 ? 0 10 70 60 50 40 30 20 10 0 c l = 0.22 f c l = 0.1 f c l = 0.047 f v s = 2.5v a v = 1 capacitive load (pf) overshoot (%) 80 70 60 50 40 30 20 10 0 10 1000 10000 100000 LT1218/19 ?tpc20 100 a v = 1 a v = 5 a v = 10 v s = 2.5v open-loop gain, v s = 15v thd + noise vs frequency output voltage (v) ?0 offset voltage change ( v) 20 LT1218/19 ?tpc23 ?0 0 10 40 30 20 10 0 10 20 30 ?0 ?5 ? 5 15 r l = 10k r l = 2k v s = 15v frequency (khz) 0.01 0.001 thd + noise (%) 0.01 0.1 1 0.1 1 10 LT1218/19 ?tpc25 v s = 1.5v v in = 2v p-p r l = 10k a v = 1 a v = 1 input offset drift vs time time after power-up (sec) change in offset voltage ( v) 40 30 20 10 0 10 20 30 ?0 LT1218/19 ?tpc24 0 20 40 60 80 100 120 140 180 200 160 v s = 15v v s = 2.5v c l = 0.22 f c l = 0.1 f load current (ma) ?0 overshoot (%) 5 LT1218/19 ?tpc22 ? 0 10 70 60 50 40 30 20 10 0 c l = 0.047 f v s = 15v a v = 1
11 LT1218/lt1219 typical perfor m a n ce characteristics u w thd + noise vs peak-to-peak voltage large-signal response v s = 15v input voltage (peak-to-peak) thd + noise (%) 10 1 0.1 0.01 0.001 024 35 LT1218/19 ?tpc26 1 v s = 1.5v a v = 1 v s = 2.5v a v = 1 v s = 2.5v a v = ? v s = 1.5v a v = ? f = 1khz r l = 10k (all curves) small-signal response v s = 15v a v = 1 v s = 15v LT1218/18 ? tpc27 a v = 1 v s = 15v LT1218/18 ? tpc28 applicatio n s i n for m atio n wu u u rail-to-rail operation the LT1218/lt1219 differ from conventional op amps in the design of both the input and output stages. figure 1 shows a simplified schematic of the amplifier. the input stage consists of two differential amplifiers, a pnp stage q1/q2 and an npn stage q3/q4, which are active over different portions of the input common mode range. lateral devices are used in both input stages, eliminating the need for clamps across the input pins. each input stage is trimmed for offset voltage. a complementary output configuration (q23 through q26) is employed to create an q24 d7 q23 q25 v v v v + v + v + v + v c1 c2 q26 d8 q22 q21 d6 q17 q16 q18 q15 q19 q20 d5 d4 d7 q11 i1 q10 q14 c c q13 q9 q8 q7 d2 q1 q2 q5 d1 q3 q4 q6 d3 q12 out v + ?300mv v + v in + in LT1218/19 ?f01 trim shdn bias control figure 1. LT1218 simplified schematic diagram
12 LT1218/lt1219 applicatio n s i n for m atio n wu u u output stage with rail-to-rail swing. the amplifier is fabri- cated on linear technologys proprietary complementary bipolar process, which ensures very similar dc and ac characteristics for the output devices q24 and q26. a simple comparator q5 steers current from current source i 1 between the two input stages. when the input common mode voltage v cm is near the negative supply, q5 is reverse biased, and i 1 becomes the tail current for the pnp differential pair q1/q2. at the other extreme, when v cm is within about 1.3v from the positive supply, q5 diverts i 1 to the current mirror d3/q6, which furnishes the tail current for the npn differential pair q3/q4. the collector currents of the two input pairs are combined in the second stage, consisting of q7 through q11. most of the voltage gain in the amplifier is contained in this stage. differential amplifier q14/q15 buffers the output of the second stage, converting the output voltage to differ- ential currents. the differential currents pass through current mirrors d4/q17 and d5/q16, and are converted to differential voltages by q18 and q19. these voltages are also buffered and applied to the output darlington pairs q23/q24 and q25/q26. capacitors c1 and c2 form local feedback loops around the output devices, lowering the output impedance at high frequencies. input offset voltage since the amplifier has two input stages, the input offset voltage changes depending upon which stage is active. the input offsets are random, but bounded voltages. when the amplifier switches between stages, offset volt- ages may go up, down or remain flat; but will not exceed the guaranteed limits. this behavior is illustrated in three distribution plots of input offset voltage in the typical performance characteristics section. overdrive protection two circuits prevent the output from reversing polarity when the input voltage exceeds the common mode range. when the noninverting input exceeds the positive supply by approximately 300mv, the clamp transistor q12 (fig- ure 1) turns on, pulling the output of the second stage low, which forces the output high. for input below the negative supply, diodes d1 and d2 turn on, overcoming the satu- ration of the input pair q1/q2. when overdriven, the amplifier draws input current that exceeds the normal input bias current. figures 2 and 3 show typical input current as a function of input voltage. the input current must be less than 10ma for the phase reversal protection to work properly. when the amplifier is severely overdriven, an external resistor should be used to limit the overdrive current. common mode voltage relative to negative supply (mv) 800 ?10 input bias current (na) ?0 ?0 ?0 ?0 600 400 LT1218/19 ?f03 200 ?0 0 ?0 ?0 ?0 ?0 ?00 v s 200 t = 55 c t = 25 c t = 85 c + t = 70 c measured as a follower figure 3. input bias current vs common mode voltage common mode voltage relative to positive supply (mv) 500 0 input bias current (na) 20 40 60 80 300 100 v s LT1218/19 ?f02 100 100 110 90 70 50 30 10 300 500 t = 55 c t = 25 c t = 85 c t = 70 c measured as a follower + figure 2. input bias current vs common mode voltage
13 LT1218/lt1219 shutdown the biasing of the LT1218/lt1219 is controlled by the shdn pin. when the shdn pin is low, the part is shut down. in the shutdown mode, the output looks like a 40pf capacitor and the supply current is less than 30 m a. the shdn pin is referenced to the positive supply through an internal bias circuit (see figure 1). the shdn pin current with the pin low is typically 3 m a. the switching time between the shutdown and active states is about 20 m s, however, the total time to settle will be greater by the slew time of the amplifier. for example, if the dc voltage at the amplifier output is 0v in shutdown and C2v in the active mode, an additional 20 m s is required. figures 4a and 4b show the switching waveforms for a sinusoidal and a C2v dc input to the LT1218. the shdn pin can be driven directly from cmos logic if the logic and the LT1218/lt1219 are operated from the same supplies. for higher supply operation, an interface is required. an easy way to interface between supplies is to use open-drain logic, an example is shown in figure 5. because the shdn pin is referenced to the positive supply, the logic used should have a breakdown voltage greater than the positive supply. applicatio n s i n for m atio n wu u u v out shdn r l = 10v v s = 2.5v LT1218/19 ? f04a figure 4a v out shdn r l = 10v v s = 2.5v LT1218/19 ? f04a figure 4b 0v 0v 0v 0v + ?5v 15v LT1218/ lt1219 LT1218/19 ?f05 shdn 5v shdn 74c906 figure 5. shutdown interface trim pins trim pins are provided for compatibility with other single op amps. input offset voltage can be adjusted over a 2.3mv range with a 10k potentiometer. + 2 3 4 1 8 7 10k v out v + LT1218/ lt1219 LT1218/19 ?f06 figure 6. optional offset nulling improved supply rejection in the lt1219 the lt1219 is a variation of the LT1218 offering greater supply rejection and lower high frequency output imped- ance. the lt1219 requires a 0.1 m f load capacitance for
14 LT1218/lt1219 applicatio n s i n for m atio n wu u u compensation. the output capacitance forms a filter, which reduces pickup from the supply and lowers the output impedance. this additional filtering is helpful in mixed analog/digital systems with common supplies or systems employing switching supplies. filtering also reduces high frequency noise, which may be beneficial when driving a/d converters. figures 7a and 7b show the outputs of the LT1218/lt1219 perturbed by a 200mv p-p 50khz square wave added to the positive supply. the lt1219 power supply rejection is about ten times greater than that of the LT1218 at 50khz. note the 5-to-1 scale change in the output voltage traces. the tolerance of the external compensation capacitor is not critical. the plots of overshoot vs load current in the typical performance characteristics section illustrate the effect of a capacitive load. LT1218/19 ? f07a figure 7a. LT1218 power supply rejection test LT1218/19 ? f07b figure 7b. lt1219 power supply rejection test typical applicatio n s u buffer for 12-bit a/d converter v ref + in in gnd v cc clk d out cs/shdn 1 2 3 4 8 7 6 5 ltc1285 + to m p 1 m f 0.1 m f 0.1 m f 3v v in lt1219 LT1218/19 ?ta03 high-side current source + LT1218 1k r sense 0.2 w 40k q1 mtp23p06 i load 5v < v cc < 30v 0a < i load < 1a at v cc = 5v 0ma < i load < 160ma at v cc = 30v q2 2n4340 v cc 100 w 0.0033 m f lt1004-1.2 r p 10k LT1218/19 ?ta04 v + (ac) v out v + (ac) v out
15 LT1218/lt1219 typical applicatio n s u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 0996 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** positive supply current sense + LT1218 q1 tp0610l v o = (i load )(r s ) r2 r1 () = (i load )(20 ) 1218/19 ?ta06 r s 0.2 load i load v cc r1 200 r2 20k v o dimensions in inches (millimeters) unless otherwise noted. package descriptio n u n8 package 8-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n8 0695 0.005 (0.127) min 0.100 0.010 (2.540 0.254) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 0.005 (3.302 0.127) 0.015 (0.380) min 0.018 0.003 (0.457 0.076) 0.125 (3.175) min 12 3 4 87 6 5 0.255 0.015* (6.477 0.381) 0.400* (10.160) max 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.025 0.015 +0.635 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm)
16 LT1218/lt1219 12189f lt/tp 0697 7k ? printed in usa ? linear technology corporation 1997 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 l (408) 432-1900 fax: (408) 434-0507 l telex: 499-3977 l www.linear-tech.com typical applicatio n u 8-channel, 12-bit data acquisition system with programmable gain 1218/19 ?ta05 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 20 21 22 23 24 1 2 3 64r 32r 16r 8r 4r 2r r r + 8 com 18 muxout gnd 4, 9 10 6 5, 14 11 7 csadc csmux clk d out d in 12 13 nc nc 12-bit sampling adc 8-channel mux 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1391 8-channel mux 5v 1 m f adcin 17 16 15, 19 1 m f 0.1 m f 5v 1 m f 5v v ref v cc + ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 v + d v d out d in cs clk gnd lt1219l ltc1598 m p/ m c inputs gain mux channel gain 0 1 1 2 2 4 3 8 4 16 5 32 6 64 7 128 part number description comments ltc ? 1152 rail-to-rail input and output, zero-drift op amp high dc accuracy, 10 m v v os(max) , 100nv/ c drift, 0.7mhz gbw, 0.5v/ m s slew rate, maximum supply current 3ma lt1366/lt1367 dual/quad precision, rail-to-rail input and output 475 m v v os(max) , 400khz gbw, 0.13v/ m s slew rate, op amps maximum supply current 520 m a per op amp lt1466/lt1467 dual/quad micropower, rail-to-rail input and output maximum supply current 75 m a per op amp, 390 m v v os(max) , op amps 120khz gain bandwidth related parts

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